Review on FPGA Implementation of 16*16 Vedic Multiplier in VHDL Environment

N. Divya

Title:
Review on FPGA Implementation of 16*16 Vedic Multiplier in VHDL Environment

Authors:
N. Divya
DOI:
https://doi.org/10.31142/ijtsrd7185

Cite This Article :

N. Divya "Review on FPGA Implementation of 16*16 Vedic Multiplier in VHDL Environment" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-2, February 2018, pp.1132-1134, URL: https://www.ijtsrd.com/papers/ijtsrd7185.pdf

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Abstract :
Multipliers are the main key components of many high performance systems such as FIR filters, Microprocessors, Digital Signal Processors, ALU and etc.It improves the speed of the many processors. Vedic mathematics is mainly based on sixteen principles or word-formulae which are termed as Sutras .A high speed complex 16 *16 multiplier design by using urdhvatiryakbhyam sutra is used here, By using this sutra the partial products and sums are generated in one step which there by reduces the design of architecture in processors. It can be used in the applications such as convolution, Fast Fourier Transform (FFT) and in microprocessors. The propagation delay of the processors can be reduced by using this technology.

Keywords :
FIR filters, ALU, Fast Fourier Transform, urdhvatriyakbhyam sutra, Digital Signal Processors

Publication Details:

Unique Identification Number : IJTSRD7185

Published In : Volume-2 | Issue-2, February 2018

Page Number(s) : 1132-1134

Publisher Name : IJTSRD | www.ijtsrd.com | E-ISSN 2456-6470

Copyright © 2019 by author(s) and International Journal of Trend in Scientific Research and Development Journal. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0) (http://creativecommons.org/licenses/by/4.0)

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