Home > Engineering > Electronics & Communication Engineering > Volume-2 > Issue-2 > Design of Dual Pulsating Latch Flip-Flop (DPLFF) using Novel Pulse Generator

Design of Dual Pulsating Latch Flip-Flop (DPLFF) using Novel Pulse Generator

Call for Papers

Volume-8 | Issue-6

Last date : 27-Dec-2024

Best International Journal
Open Access | Peer Reviewed | Best International Journal | Indexing & IF | 24*7 Support | Dedicated Qualified Team | Rapid Publication Process | International Editor, Reviewer Board | Attractive User Interface with Easy Navigation

Journal Type : Open Access

First Update : Within 7 Days after submittion

Submit Paper Online

For Author

Research Area


Design of Dual Pulsating Latch Flip-Flop (DPLFF) using Novel Pulse Generator


Surbhi Vishwakarma | Dr. Vinod Kapse

https://doi.org/10.31142/ijtsrd12743



Surbhi Vishwakarma | Dr. Vinod Kapse "Design of Dual Pulsating Latch Flip-Flop (DPLFF) using Novel Pulse Generator" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-2, February 2018, pp.1713-1718, URL: https://www.ijtsrd.com/papers/ijtsrd12743.pdf

In this paper various flip-flop structures have been studied. In all designs to reduce power consumption, the Pulse Generator circuitry should be in build along with the flip-flop itself. If a pulse generator is included along with DPSCRFF structure, power consumption can be reduced. In this work a new design of flip-flop, Double Pulse Latch Flip-flop (DPLFF) is proposed. DPLFF eliminates unnecessary glitches, which consume more power. DPLFF consume less power for same delay as compared with other existing techniques, which is performing one of the fastest known flip-flops. In serial operation as shift register the proposed DPLFF can perform better at the higher frequency. The stacking of transistor in the latch stage cause reduction in subthreshold leakage current & thus the static power consumption is also less for DPLFF. This is better suited for low power circuits at deep submicron technology where leakages are more dominant.

DPLFF, Delay, Power Consumption, Speed, Latch, Flip-flop, Pulse Generator


IJTSRD12743
Volume-2 | Issue-2, February 2018
1713-1718
IJTSRD | www.ijtsrd.com | E-ISSN 2456-6470
Copyright © 2019 by author(s) and International Journal of Trend in Scientific Research and Development Journal. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0) (http://creativecommons.org/licenses/by/4.0)

International Journal of Trend in Scientific Research and Development - IJTSRD having online ISSN 2456-6470. IJTSRD is a leading Open Access, Peer-Reviewed International Journal which provides rapid publication of your research articles and aims to promote the theory and practice along with knowledge sharing between researchers, developers, engineers, students, and practitioners working in and around the world in many areas like Sciences, Technology, Innovation, Engineering, Agriculture, Management and many more and it is recommended by all Universities, review articles and short communications in all subjects. IJTSRD running an International Journal who are proving quality publication of peer reviewed and refereed international journals from diverse fields that emphasizes new research, development and their applications. IJTSRD provides an online access to exchange your research work, technical notes & surveying results among professionals throughout the world in e-journals. IJTSRD is a fastest growing and dynamic professional organization. The aim of this organization is to provide access not only to world class research resources, but through its professionals aim to bring in a significant transformation in the real of open access journals and online publishing.

Thomson Reuters
Google Scholer
Academia.edu

ResearchBib
Scribd.com
archive

PdfSR
issuu
Slideshare

WorldJournalAlerts
Twitter
Linkedin