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Floating Point Operations Compatible Streaming Elements for FPGA Accelerators

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Floating Point Operations Compatible Streaming Elements for FPGA Accelerators


Chinta Sravani | Dr. Prasad Janga | Mrs. S. SriBindu

https://doi.org/10.31142/ijtsrd15853



Chinta Sravani | Dr. Prasad Janga | Mrs. S. SriBindu "Floating Point Operations Compatible Streaming Elements for FPGA Accelerators" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-5, August 2018, pp.302-309, URL: https://www.ijtsrd.com/papers/ijtsrd15853.pdf

We see that in most computers and applications the CPU is taxed, first and foremost, before other pieces of hardware are. As this is seen in most general usage cases, especially if someone has a strong CPU, there are others where it might be smart for your computer to use other components in your system. This is where hardware acceleration comes into play. In computing, hardware acceleration is the use of computer hardware to perform some functions more efficiently than is possible in software running on a more general-purpose CPU. To perform operations at high speeds we require accelerators which can boost the speed of the circuit. In order to achieve this, we have custom circuits where flexibility of the circuit is not possible and soft process approach where there is only register to register transfer is present. To overcome these faults in the existing system a high-performance, fine grained streaming processor, known as a streaming accelerator element, is proposed which realizes accelerators as large-scale custom multicore networks. By implementing this approach with advanced program control and memory addressing capabilities, we can see that the program inefficiencies can be almost eliminated to enable performance and cost, which are not possible among other software-programmable solutions. When used to realize accelerators for matrix multiplication it is shown how the proposed architecture enables real-time performance. To support floating point operations we add Floating Point Unit (FPU) to the ALU of processing elements which performs IEEE754 2008 single precision floating point operations addition, multiplication, and subtraction.

Accelerators, Field Programmable Gate Array (FPGA), Streaming Elements, Floating Point, Matrix Multiplication


IJTSRD15853
Volume-2 | Issue-5, August 2018
302-309
IJTSRD | www.ijtsrd.com | E-ISSN 2456-6470
Copyright © 2019 by author(s) and International Journal of Trend in Scientific Research and Development Journal. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0) (http://creativecommons.org/licenses/by/4.0)

International Journal of Trend in Scientific Research and Development - IJTSRD having online ISSN 2456-6470. IJTSRD is a leading Open Access, Peer-Reviewed International Journal which provides rapid publication of your research articles and aims to promote the theory and practice along with knowledge sharing between researchers, developers, engineers, students, and practitioners working in and around the world in many areas like Sciences, Technology, Innovation, Engineering, Agriculture, Management and many more and it is recommended by all Universities, review articles and short communications in all subjects. IJTSRD running an International Journal who are proving quality publication of peer reviewed and refereed international journals from diverse fields that emphasizes new research, development and their applications. IJTSRD provides an online access to exchange your research work, technical notes & surveying results among professionals throughout the world in e-journals. IJTSRD is a fastest growing and dynamic professional organization. The aim of this organization is to provide access not only to world class research resources, but through its professionals aim to bring in a significant transformation in the real of open access journals and online publishing.

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