In this paper we have proposed efficient designs of low power high speed D-latch designed using stacked inverter and sleep transistor based on 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W/L ratio of each transistor in the circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product.
CMOS, Clock, Latch, Power Delay Product, MOSFET
International Journal of Trend in Scientific Research and Development - IJTSRD having
online ISSN 2456-6470. IJTSRD is a leading Open Access, Peer-Reviewed International
Journal which provides rapid publication of your research articles and aims to promote
the theory and practice along with knowledge sharing between researchers, developers,
engineers, students, and practitioners working in and around the world in many areas
like Sciences, Technology, Innovation, Engineering, Agriculture, Management and
many more and it is recommended by all Universities, review articles and short communications
in all subjects. IJTSRD running an International Journal who are proving quality
publication of peer reviewed and refereed international journals from diverse fields
that emphasizes new research, development and their applications. IJTSRD provides
an online access to exchange your research work, technical notes & surveying results
among professionals throughout the world in e-journals. IJTSRD is a fastest growing
and dynamic professional organization. The aim of this organization is to provide
access not only to world class research resources, but through its professionals
aim to bring in a significant transformation in the real of open access journals
and online publishing.