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Implementation of 8x8 Vedic Multiplier using Verilog

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Implementation of 8x8 Vedic Multiplier using Verilog


Mr. Parasurama | Singamsetti Raviteja | Mohamad Shajahan



Mr. Parasurama | Singamsetti Raviteja | Mohamad Shajahan "Implementation of 8x8 Vedic Multiplier using Verilog" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-2, April 2024, pp.808-815, URL: https://www.ijtsrd.com/papers/ijtsrd64769.pdf

A Multiplier is one of the key hardware blocks in most fast processing system which requires less power dissipation. A conventional multiplier consumes more power. This paper presents a low power 8 bit Vedic. Multiplier (VM) based on Vertically & Crosswise method of Vedic mathematics; a general multiplication formulae equally applicable to all cases of multiplication. It is based on generating all partial products and their sum in one step. The implementation is done using cadence Virtuoso tool. The power dissipation of 8x8 bit Vedic multiplier obtained after synthesis is compared with conventional multipliers such as Wallace tree and array multipliers and found that the proposed Vedic multiplier circuit seems to have better performance in terms of power dissipation. The essential persistence of this project is to advance the swiftness of the digital circuits like multiplier, meanwhile the multiplier and adder stay unique of the crucial hardware modules in an extraordinary performance systems like DSP (digital signal processors), microprocessors and FIR filters etc. Vedic multiplier is alone such extraordinary and swift multiplier architecture. This Vedic Mathematics is the forename specified to the original system of mathematics. It has a sole process of calculations founded on 16 Sutras. The multiplication sutra midst these 16 sutras is the Urdhva Tiryakbhyam sutra which means upright and diagonal. The projected system is designed using Verilog and it is fulfilled over Xilinx ISE 14.2.

URDHVATIRYAKBHYAM, FPGA, RSIC


IJTSRD64769
Volume-8 | Issue-2, April 2024
808-815
IJTSRD | www.ijtsrd.com | E-ISSN 2456-6470
Copyright © 2019 by author(s) and International Journal of Trend in Scientific Research and Development Journal. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0) (http://creativecommons.org/licenses/by/4.0)

International Journal of Trend in Scientific Research and Development - IJTSRD having online ISSN 2456-6470. IJTSRD is a leading Open Access, Peer-Reviewed International Journal which provides rapid publication of your research articles and aims to promote the theory and practice along with knowledge sharing between researchers, developers, engineers, students, and practitioners working in and around the world in many areas like Sciences, Technology, Innovation, Engineering, Agriculture, Management and many more and it is recommended by all Universities, review articles and short communications in all subjects. IJTSRD running an International Journal who are proving quality publication of peer reviewed and refereed international journals from diverse fields that emphasizes new research, development and their applications. IJTSRD provides an online access to exchange your research work, technical notes & surveying results among professionals throughout the world in e-journals. IJTSRD is a fastest growing and dynamic professional organization. The aim of this organization is to provide access not only to world class research resources, but through its professionals aim to bring in a significant transformation in the real of open access journals and online publishing.

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